(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to a method of forming self-aligned silicide with reduced sheet resistance in the manufacture of an integrated circuit device.
(2) Description of the Prior Art
Metal silicides, or simply, silicides, are formed by the reaction of a metal layer, such as titanium or cobalt, with silicon or polysilicon. In MOS processes of the current art, silicide layers are used to reduce the resistivity of polysilicon lines and the contact resistance of polysilicon gates and silicon source and drain regions. A particular type of silicide process is called self-aligned silicide, or salicide. In a salicide process, the silicide layer is selectively formed on, for example, the polysilicon gates and the silicon source and drain regions, without a silicide masking or etching step. The salicide process offers the benefits of silicide with little additional processing complexity.
Referring now to FIG. 1, a prior art salicide process is illustrated. An MOS transistor is formed overlying a semiconductor substrate 10. In a typical processing sequence, a gate oxide layer 18 and a polysilicon layer 22 are deposited overlying the semiconductor substrate 10. The polysilicon layer 22 and the gate oxide layer 18 are patterned to form the gate for the MOS device. Lightly doped drain (LDD) implants are then performed self-aligned to the gate 22 and the shallow trench isolations (STI) 14. Sidewall spacers 30 are then formed from a dielectric material. The heavily doped source and drain implants are then performed self-aligned to the sidewall spacers 30 and the STI 14 to complete the source and drain regions 26. A metal layer 34, such as titanium or cobalt, is then deposited overlying the gate 22, sidewall spacers 30, source and drain regions 26, and STI 14 as shown.
Referring now to FIG. 2, the integrated circuit wafers are then subjected to a high temperature annealing process. During the anneal, the metal layer 34 reacts with the polysilicon layer 22 and the silicon of the semiconductor substrate 10 (in the source and drain regions 26) to form metal silicide 38 and 42. After the anneal, unreacted metal layer 34 is removed in a wet chemical rinse.
The key advantage of the salicide process can be seen. The metal silicide layer 38 and 42 has formed only in the polysilicon gate 22 and the source and drain regions 26, respectively. No masking step was used. Therefore, the silicide is said to have formed in a self-aligned fashion. The presence of the metal silicide layer 38 and 42 reduces the contact resistance of both the polysilicon gate 22 and the source and drain regions 26. In addition, the metal silicide 38 reduces the sheet resistance of the polysilicon 22.
As MOS processes continue to shrink, the critical dimension (CD) for the polysilicon lines 22 is reduced. The width L1 of the polysilicon lines 22, determines the length of the MOS transistors. By reducing transistor length, packing densities and switching speeds can be increased. However, as the width L1 of the polysilicon lines 22 has been reduced, the sheet resistance of the salicided polysilicon has increased. Keeping the sheet resistance of the salicided polysilicon low while shrinking the width to the deep sub-micron regime is an important challenge in the art.
Several prior art approaches disclose methods to form self-aligned silicide in the manufacture of integrated circuit devices. U.S. Pat. No. 5,913,124 to Lin et al discloses a method to form self-aligned silicide for MOS transistors. A tilt-angle ion implant is used to deepen the source and drain regions near the STI regions. The STI are over-etched during the gate spacer etch to create additional silicide contact area. U.S. Pat. No. 5,923,986 to Shen teaches a self-aligned silicide method. After formation of first gate spacers, additional xe2x80x9c0.5xe2x80x9d spacers are formed on the first gate spacers. The combined spacer profile forms a discontinuous step that prevents the formation of silicide shorts. U.S. Pat. No. 5,208,472 to Su et al discloses a self-aligned silicide process. A double layered sidewall spacer is used to create the LDD and source/drain offsets and to improve the process capability. U.S. Pat. No. 5,668,065 to Lin teaches a process to simultaneously form self-aligned contacts, silicide, and local interconnects. An amorphous silicon layer is selectively deposited and then converted to silicide. U.S. Pat. No. 5,747,373 to Yu discloses a self-aligned silicide process. A double layer sidewall is formed using silicon dioxide and silicon nitride. U.S. Pat. No. 5,869,369 to Pan et al shows a polycide gate electrode process.
A principal object of the present invention is to provide an effective and very manufacturable method to form self-aligned silicide in the manufacture of integrated circuits.
A further object of the present invention is to provide a method to increase the silicide layer surface area in polysilicon lines and to thereby reduce the sheet resistivity of those polysilicon lines.
Another further object of the present invention is to form an improved self-aligned silicide by forming unique dielectric sidewall spacers using a polish down of the dielectric layer before etching the dielectric sidewall spacers.
Yet another object of the present invention is to provide a self-aligned silicide MOS transistor device with improved gate resistance.
In accordance with the objects of this invention, a new method of forming MOS transistors with self-aligned silicide in the manufacture of an integrated circuit device has been achieved. A semiconductor substrate is provided. A gate oxide layer is formed overlying the semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. The polysilicon layer and the gate oxide layer are patterned to form gates. Ions are implanted into the semiconductor substrate to form lightly doped drain regions. A dielectric layer is deposited overlying the gates and the semiconductor substrate. The dielectric layer is polished down to expose the top surface of the gates. The dielectric layer is then anisotropically etched down to form dielectric sidewall spacers. The dielectric sidewall spacers cover a portion of the vertical sidewalls of the gates while exposing a portion of the vertical sidewalls of the gates. Ions are implanted into the semiconductor substrate to form source and drain regions. A metal layer is deposited overlying the gates, the dielectric sidewall spacers, and the semiconductor substrate. Contact surfaces are formed between the metal layer and the exposed top surfaces of the gates, between the metal layer and the exposed portions of the vertical sidewalls of the gates, and between the metal layer and the semiconductor substrate in the source and drain regions. The integrated circuit device is annealed to react the metal layer and the polysilicon layer and to react the metal layer and the semiconductor substrate to selectively form a silicide layer in the surface of the polysilicon layer and in the surface of the semiconductor substrate at the contact surfaces. The remaining metal layer is removed to complete the MOS transistors with self-aligned silicide in the manufacture of the integrated circuit device.
Also in accordance with the objects of this invention, a self-aligned silicide MOS transistor device is achieved. A gate comprises first a gate oxide layer overlying a semiconductor substrate. A polysilicon layer overlies the gate oxide layer. Dielectric sidewall spacers cover a portion of the vertical sidewalls of the polysilicon layer while exposing a portion of the vertical sidewalls of the polysilicon layer. A silicide layer is in the surface of the exposed portions of the vertical sidewalls and in the top surface of the polysilicon layer to complete the gate. The drain and source junctions each comprise first a lightly doped drain region in the semiconductor substrate. The lightly doped drain region is self-aligned to the polysilicon layer. A heavily doped region is in the semiconductor substrate. The heavily doped region is self-aligned to the dielectric sidewall spacers. A silicide layer is in the surface of the heavily doped region to complete the source and drain junctions.